Sunday, March 6, 2011
Optimized code a little bit
I've optimized the AVR code a little bit so that the timing for when the disk drive is sending a "clock" signal is now really tight and I am getting the correct results. Since the AVR is clocked at 14.7456 MHz (so that it can send serial communications reliably), 1 microsecond is about 0xE cycles, and I am alternating between 0xC and 0xF cycles in my tests which is exactly what I would expect. Unfortunately, the lengths after the "1" bit are too long. Each bit field is 4 microseconds long, which is about 0x3A cycles, so I should be seeing values near 0x2C at least every 8 bits (because every nibble on the drive has the high bit set).
I'm not seeing that, so I'm wondering if I am missing the transition due to some of my code being too slow.