Sunday, February 2, 2014
Better CSYNC capture
The green line is supposed to match the red line. The yellow line represents an intermediate state.
Red high to low transition:
The yellow line's initial lag of the red line is caused (in my opinion) by our use of a 10k pull-up resistor. Decrease the resistance may improve the timing here. The green line changes at the same time as the yellow line because we are using an open-collector NAND gate which goes low super-fast (much faster than it goes high).
Red low to high transition:
The yellow line responds "instantly" to the red's change here because again, we are using an open-collector NAND gate which responds much faster when going low (which the yellow line is doing in this case). However, since it's time for the green line to go high, it is very slow because it is using the AVR's internal pull-up resistor which has more resistance (apparently) than 10k. You may look at the timing and think "Ahh, it's just a few microseconds off, it won't matter" but I have yet to arrive at this conclusion.
I think it may be important to tweak this solution to try to get the green line more in sync with the red line.