star rider 13 feb 2014

Star Rider emulation progress

Got most of the ROM tests passing, two of them are still failing.
Colors are not correct, I just did a rough hack for the color palette.

Star Rider boot

Got Star Rider booting inside Daphne.  Don't have blitter chips (or the ROM PCB) emulated yet so this is as far as it's gonna go for a while.

Star Rider VGG timers

If you designed this timer system, in 6 months, would you really be able to explain how it worked? :)

These were really hard to get because the design (and hence schematic) is a huge mess (I don't even know if the designers of the game knew what half of this crap did) and the timings came from a PROM.  In other words, figuring this out by hand is really hard (I foolishly made an attempt).  I ended up writing a little C program to figure it out for me which was a lot easier.  The above graph is the results of my C program.

UPDATE: Warren got a capture on real hardware and it matches my emulated version perfectly! :)

A few observations:

• The main 6809E CPU runs at 1 MHz.  This was what I assumed for a long time but now I've "proven" it for sure.
• The 4 MHz signal does not have a smooth rhythm.  I had also assumed this since it gets derived from the 6 MZ clock.  Had they derived it from the 12 MHz clock, they could've got the rhythm smooth.  I assume that despite the unusual cadence that it still performs its function just fine (controlling the blitters).
• Plugging in the laserdisc video signal will throw these timers off temporarily.  The game has a (pretty neat) mechanism to sync up to the laserdisc's video.  Once in sync, I assume the timers will resume normal operation  (not confirmed).
• Despite Q2 and CAS' being slightly different on the schematic, they appear to be identical in practice (at least as long as the laserdisc video input is not plugged in)
• Same thing with Q7 and 4 MHz.  Q7 is connected to the 4 MHz flip-flop's clear pin, but this seems to have no effect (either that or I made a mistake).
• LATCH seems intended to begin after E and end before E.
• RAS' and CAS' are used to keep the video DRAM chips from losing their state.  What a horrid thing to have to deal with from a designer's perspective :)

How to calculate the duration of NTSC lines and fields

I don't want to have to figure this out again, so here is the "exact" length of one horizontal line in microseconds.  If you want seconds, remove the 1,000,000 number.

H = (1001 * 1000000 * 2) / (1000 * 60 * 525)

(this can be simplified down to 4004/63)

The "exact" length of one field (ie space between start of two adjacent vsync pulses) in microseconds is:

V = (1001 * 1000000) / (1000 * 60)

(simplified down to 50050/3)

Physics/Engineering question (Composite sync to Vertical/Horizontal sync)

I remember learning some equations about capacitors in school but I've long since forgotten this stuff and now I find that it would actually be useful for solving the below problem.

Here is how the game, Star Rider, derives vertical and horizontal sync by getting a composite sync input.  My question is, how?  How can one solve this on paper and predict when vsync and hsync will go low by only knowing the timing to csync and the resistance and capacitor values of this circuit?

The timing to csync (composite sync) is shown here (item 'b'):

Csync will either be 5V or ground.

Here is the circuit used in Star Rider:

W3 is connected, W4 is unconnected.  All of the NOT gates are a 74LS14.

Testing response performance of solid state relay

So in my last blog post, I tested how responsive passing CSYNC was when passed through two open collector NAND gates.  As you may have noticed, there was some delay due to the pull-up resistors we were using.  So last night, I decided to test out how responsive passing CSYNC through a solid state relay would be.  I did have a couple of extra solid state relays from when Dexter rev2 was built, but unfortunately, they are surface mount, so they are not very bread board friendly.

I decided to try to solder wires to the legs of the relay since it only has 4 legs.

My first attempt was disastrous because I used too thick of wires and it broke off one of the legs.  Fortunately, I had two of these things!

My second attempt involved using much thinner wire, soldered to the thick stuff, and then inserted in the bread board.  It worked, although it did take me a VERY LONG time to get the wires soldered to the legs.

The big question is, how did it perform?

Very well!  In fact, even capturing at the maximum stable frequency, I was not able to see any lag from the source CSYNC and the CSYNC signal coming out of the relay.